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Disambiguation of "Park, Hojin"

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An Asynchronous Boost Converter With Time-Based Dual-Mode Control for Wide Load Range and High Efficiency in SSD Applications.

, , , , , , , and . IEEE Trans. Ind. Electron., 67 (12): 10520-10530 (2020)

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Hojin Kee

Sungjune Park

Rosemary Park

Jinhyung Park

Kwan Park

 

Other publications of authors with the same name

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS., , , , and . ISSCC, page 328-329. IEEE, (2016)A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range., , , , , and . ISSCC, page 250-251. IEEE, (2013)A 0.015-mm2 Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 64-II (6): 655-659 (2017)Open-Set Face Identification on Few-Shot Gallery by Fine-Tuning., , and . CoRR, (2023)More IOPS for Less: Exploiting Burstable Storage in Public Clouds., , and . HotCloud, USENIX Association, (2020)15.5 A 0.6V 1.17ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET technology., , , , , and . ISSCC, page 1-3. IEEE, (2015)A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter., , , , , , , , and . ISSCC, page 254-255. IEEE, (2013)Verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization., , , , , and . ICCAD, page 486-493. IEEE, (2013)Layout Synthesis and Loop Parameter Optimization of a Low-Jitter All-Digital Pixel Clock Generator., , , and . IEEE J. Solid State Circuits, 49 (3): 657-672 (2014)Design of a Digital Home Service Delivery and Management System for OSGi Framework., , and . APNOMS, volume 4773 of Lecture Notes in Computer Science, page 1-10. Springer, (2007)