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A Multilevel Congestion-Based Global Router.

, , , и . VLSI Design, (2009)

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Meenakshi B Loganathan

Paul E Logan

Emily Máire Logan

Sivakkanan Loganathan

Simon M M Laimer

 

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A Multilevel Congestion-Based Global Router., , , и . VLSI Design, (2009)Wirelength and congestion estimation for routability-driven placement., , , и . SLIP, стр. 1. IEEE Computer Society, (2011)Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes., , , и . ISPD, стр. 154-161. ACM, (2013)A fast force-directed simulated annealing for 3D IC partitioning., , , и . Integr., (2016)Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (4): 532-545 (2014)A pre-placement net length estimation technique for mixed-size circuits., , и . SLIP, стр. 45-52. ACM, (2009)A self-tuning multi-objective optimization framework for geometric programming with gate sizing applications., , , и . ACM Great Lakes Symposium on VLSI, стр. 305-310. ACM, (2013)Optimal gate sizing using a self-tuning multi-objective framework., , , и . Integr., 47 (3): 347-355 (2014)GPU-Accelerated Solutions to Optimal Power Flow Problems., и . HICSS, стр. 2511-2516. IEEE Computer Society, (2014)An algebraic multigrid-based algorithm for circuit clustering., , , и . Appl. Math. Comput., 218 (9): 5202-5216 (2012)