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Disambiguation of "Park, Kwang-Il"

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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques.

, , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 55 (1): 157-166 (2020)

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Kwang Park

Sun-Kwang Park

Kwang Woo Park

Kwang-jack Park

Kwang-Ki Park

 

Other publications of authors with the same name

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces., , , , and . IEEE J. Solid State Circuits, 44 (5): 1522-1530 (2009)A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration., , , , , , , , , and 14 other author(s). VLSI Circuits, page 114-. IEEE, (2019)A Wormhole Router with Embedded Broadcasting Virtual Bus for Mesh Computers., , , and . Parallel Process. Lett., 10 (1): 29-37 (2000)HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors., , , , , and . Int. J. Distributed Sens. Networks, (2013)A DLL with Jitter-Reduction Techniques for DRAM Interfaces., , , , and . ISSCC, page 496-497. IEEE, (2007)A Methodology Combining Cosine Similarity with Classifier for Text Classification., , and . Applied Artificial Intelligence, 34 (5): 396-411 (2020)A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme., , , , , and . IEEE J. Solid State Circuits, 44 (8): 2222-2232 (2009)A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 50 (1): 178-190 (2015)Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond., , , , , , , , , and 10 other author(s). HCS, page 1-26. IEEE, (2021)Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM., , , , , , and . DAC, page 91:1-91:6. ACM, (2015)