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Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.

, , , and . ACM Great Lakes Symposium on VLSI, page 19-24. ACM, (2001)

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Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization., , , and . EDAC-ETC-EUROASIC, page 490-494. IEEE Computer Society, (1994)Quadratic zero-one programming-based synthesis of application-specific data paths., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (1): 1-11 (1995)Processor modeling and code selection for retargetable compilation., , , and . ACM Trans. Design Autom. Electr. Syst., 6 (3): 277-307 (2001)Quadratic zero-one programming based synthesis of application specific data paths., , and . ICCAD, page 522-525. IEEE Computer Society / ACM, (1993)A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report., , , , , , , , , and 2 other author(s). CoRR, (2013)Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing., , and . DAC, page 124-127. IEEE Computer Society Press, (1992)Embedded software in real-time signal processing systems: design technologies., , , , , , and . Proc. IEEE, 85 (3): 436-454 (1997)A Graph Based Processor Model for Retargetable Code Generation., , , , and . ED&TC, page 102-107. IEEE Computer Society, (1996)ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces., , , , , , , , , and 2 other author(s). Future Gener. Comput. Syst., (2015)Chess: retargetable code generation for embedded DSP processors., , , , , , and . Code Generation for Embedded Processors, page 85-102. Kluwer, (1994)