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Applying Caching to Two-Level Adaptive Branch Prediction.

, , , and . DSD, page 186-193. IEEE Computer Society, (2001)

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An Extension of the VSM Documents Representation., , , and . Int. J. Comput. Commun. Control, 12 (3): 402-414 (2017)Extending Correlation in Branch Prediction Schemes., and . EUROMICRO, page 1441-1448. IEEE Computer Society, (1999)Cached Two-Level Adaptive Branch Predictors with Multiple Stages., , and . ARCS, volume 2299 of Lecture Notes in Computer Science, page 179-194. Springer, (2002)Two-level branch prediction using neural networks., , , , , and . J. Syst. Archit., 49 (12-15): 557-570 (2003)Exploiting selective instruction reuse and value prediction in a superscalar architecture., , and . J. Syst. Archit., 55 (3): 188-195 (2009)Towards a high performance neural branch predictor., and . IJCNN, page 868-873. IEEE, (1999)The impact of cache organisation on the instruction issue rate of a superscalar processor., , and . PDP, page 58-65. IEEE Computer Society, (1999)The Impact of Java Applications at Microarchitectural Level from Branch Prediction Perspective., , , and . Int. J. Comput. Commun. Control, 4 (1): 27-40 (2009)An alternative to branch prediction: pre-computed branches., , , and . SIGARCH Comput. Archit. News, 31 (3): 20-29 (2003)Topic 4 High-Performance Architectures and Compilers., , , and . Euro-Par, volume 4641 of Lecture Notes in Computer Science, page 235. Springer, (2007)