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Disambiguation of "Raina, Priyanka"

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Timeloop: A Systematic Approach to DNN Accelerator Evaluation.

, , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)

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Mohit Ajitkumar Raina

Robert Anton Rainalter

Priyanka Nannapaneni

Priyanka Shahi

Raina Yamamoto

 

Other publications of authors with the same name

Unified Buffer: Compiling Image Processing and Machine Learning Applications to Push-Memory Accelerators., , , , , , , and . ACM Trans. Archit. Code Optim., 20 (2): 26:1-26:26 (June 2023)AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers., , , , , , , , , and 23 other author(s). ACM Trans. Embed. Comput. Syst., 22 (2): 35:1-35:34 (March 2023)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)Timeloop: A Systematic Approach to DNN Accelerator Evaluation., , , , , , , , , and . ISPASS, page 304-315. IEEE, (2019)CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference., , , , , , , , , and 8 other author(s). VLSI Circuits, page 1-2. IEEE, (2021)Automating Vitiligo Skin Lesion Segmentation Using Convolutional Neural Networks., , and . ISBI, page 1-4. IEEE, (2020)A-QED Verification of Hardware Accelerators., , , , , , , , , and 3 other author(s). DAC, page 1-6. IEEE, (2020)Synthesizing Instruction Selection Rewrite Rules from RTL using SMT., , , , , , , and . FMCAD, page 139-150. IEEE, (2022)Best Papers From Hot Chips 32., and . IEEE Micro, 41 (2): 6 (2021)Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 59 (3): 947-959 (March 2024)