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Disambiguation of "Thanailakis, Antonios"

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Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.

, , , , , , and . WWIC, volume 3510 of Lecture Notes in Computer Science, page 354-364. Springer, (2005)

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Antonios Ananiadis

Antonios Zarkadis

Antonios Moissidis

Antonios Renkakos

Antonios Gkogkidis

 

Other publications of authors with the same name

Power, performance and area exploration of block matching algorithms mapped on programmable processors., , , , , , , and . ICIP (3), page 728-731. IEEE, (2001)Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications., , , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 540-549. Springer, (2004)Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications., , , , , , and . DATE, page 740-745. European Design and Automation Association, Leuven, Belgium, (2006)Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors., , , , , , and . J. VLSI Signal Process., 44 (1-2): 153-171 (2006)Design and simulation of a nanoelectronic single-electron universal Control-Control-Not gate., , and . Microelectron. J., 35 (5): 471-478 (2004)Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique., , and . VLSI-SoC, page 204-209. IEEE, (2006)A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck., , , , , and . DATE, page 946-947. IEEE Computer Society, (2005)A novel methodology for designing high-performance and low-energy FPGA routing architecture., , , and . FPGA, page 224. ACM, (2006)A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck, , , , , and . CoRR, (2007)Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays., , and . J. Low Power Electron., 4 (1): 34-47 (2008)