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Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip.

, , , and . Embedded Systems Design and Verification, CRC Press, (2009)

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A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication., , , , and . VLSI-SoC (Selected Papers), volume 313 of IFIP Advances in Information and Communication Technology, page 232-250. Springer, (2008)Automated Composition of Hardware Components., and . DAC, page 14-19. ACM Press, (1998)Parallel vs. serial inter-plane communication using TSVs., , and . LASCAS, page 1-5. IEEE, (2014)A study on buffer distribution for RRAM-based FPGA routing structures., , , and . LASCAS, page 1-4. IEEE, (2015)A fast pruning technique for low-power inexact Circuit design., , , , , and . LASCAS, page 1-4. IEEE, (2015)System-Level Design for Nano-Electronics., , , , and . ICECS, page 747-751. IEEE, (2007)New Design Paradigms: New Architectures for New technologies.. ICECS, page 1. IEEE, (2007)Pattern-based FPGA logic block and clustering algorithm., , and . FPL, page 1-4. IEEE, (2014)Synthesis of hardware models in C with pointers and complex data structures., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 743-756 (2001)A robust self-calibrating transmission scheme for on-chip networks., , , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (1): 126-139 (2005)