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Disambiguation of "Torres, Lionel"

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Embedded MRAM for high-speed computing.

, , , , , , , , , , , and . VLSI-SoC, page 37-42. IEEE, (2011)

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Lionel Magloire

Lionel Hernández

Lionel Untereiner

Lionel Gouyet

Lionel Winkelmann

 

Other publications of authors with the same name

Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography., , , , and . VLSI-SoC, volume 360 of IFIP Advances in Information and Communication Technology, page 135-155. Springer, (2009)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , and 3 other author(s). DATE, page 103-108. IEEE, (2018)Secure FPGA configuration architecture preventing system downgrade., , and . FPL, page 317-322. IEEE, (2008)Influence of Locig Block Layout Architecture on FPGA Performance., , , and . FPL, volume 849 of Lecture Notes in Computer Science, page 34-44. Springer, (1994)A new hardware countermeasure for masking power signatures of crypto cores., , , , , , and . ReCoSoC, page 169-176. Univ. Montpellier II, (2005)Cost-Effective Design Strategies for Securing Embedded Processors., , , , , and . IEEE Trans. Emerg. Top. Comput., 4 (1): 60-72 (2016)PoETE: A Method to Design Temperature-Aware Integrated Systems., , , , and . J. Low Power Electron., 14 (1): 1-7 (2018)Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems., , , , , and . ReCoSoC, page 69-75. Univ. Montpellier II, (2006)Integration of Reconfigurable Logic on Secure Circuits., , , and . ReCoSoC, page 163-168. Univ. Montpellier II, (2005)A Parallel and Secure Architecture for Asymmetric Cryptography., , , , , and . ReCoSoC, page 220-224. Univ. Montpellier II, (2006)