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Combinational circuit fault diagnosis using logic emulation., , , , и . ISCAS (5), стр. 549-552. IEEE, (2003)Efficient test and repair architectures for 3D TSV-based random access memories., , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs., , , и . VLSI-DAT, стр. 1-4. IEEE, (2015)A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , и . ISCIT, стр. 1-5. IEEE, (2017)A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , и . 3DIC, стр. 1-6. IEEE, (2014)Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults., , , , , и . J. Inf. Sci. Eng., 19 (4): 571-587 (2003)Fault-Aware Dependability Enhancement Techniques for Phase Change Memory., , , , и . J. Electron. Test., 37 (4): 503-513 (2021)Design-for-testability and fault-tolerant techniques for FFT processors., , и . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 732-741 (2005)Yield enhancement techniques for 3-dimensional random access memories., , и . Microelectron. Reliab., 52 (6): 1065-1070 (2012)A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs., , , , , , и . IEICE Trans. Inf. Syst., 99-D (11): 2723-2733 (2016)