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Instruction-level parallelism from execution interlock collapsing., , and . SIGARCH Comput. Archit. News, 20 (4): 38-43 (1992)Performance Evaluation of Multiple Register Sets., and . ISCA, page 264-271. (1987)On the attributes of the SCISM organization., , and . SIGARCH Comput. Archit. News, 20 (4): 44-53 (1992)Performance Evaluation of On-Chip Register and Cache Organizations., and . ISCA, page 64-72. IEEE Computer Society, (1988)A performance methodology for commercial servers., , , , , , , , and . IBM J. Res. Dev., 44 (6): 851-872 (2000)Characterization of simultaneous multithreading (SMT) efficiency in POWER5., , , , and . IBM J. Res. Dev., 49 (4-5): 555-564 (2005)IBM POWER8 processor core microarchitecture., , , , , , , , , and 10 other author(s). IBM J. Res. Dev., (2015)A multithreaded PowerPC processor for commercial servers., , , and . IBM J. Res. Dev., 44 (6): 885-898 (2000)Disaggregated and optically interconnected memory: when will it be cost effective?, , , , and . CoRR, (2015)SCISM: A scalable compound instruction set machine., , and . IBM J. Res. Dev., 38 (1): 59-78 (1994)