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Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (12): 1884-1893 (2010)

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Designing reliable analog circuits in an unreliable world., , and . CICC, page 1-4. IEEE, (2012)Hierarchical analog circuit reliability analysis using multivariate nonlinear regression and active learning sample selection., , and . DATE, page 745-750. IEEE, (2012)Efficient Variability-Aware NBTI and Hot Carrier Circuit Reliability Analysis., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (12): 1884-1893 (2010)Advances in variation-aware modeling, verification, and testing of analog ICs., , , , , and . DATE, page 1615-1620. IEEE, (2012)Stochastic degradation modeling and simulation for analog integrated circuits in nanometer CMOS., and . DATE, page 326-331. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Offset measurement method for accurate characterization of BTI-induced degradation in opamps., , , and . ICECS, page 661-664. IEEE, (2012)A methodology for measuring transistor ageing effects towards accurate reliability simulation., and . IOLTS, page 21-26. IEEE Computer Society, (2009)Computer-Aided Analog Circuit Design for Reliability in Nanometer CMOS., and . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (1): 50-58 (2011)Transistor aging-induced degradation of analog circuits: Impact analysis and design guidelines., and . ESSCIRC, page 243-246. IEEE, (2011)Stochastic circuit reliability analysis., and . DATE, page 1285-1290. IEEE, (2011)