Author of the publication

A neural network circuit with associative learning and forgetting process based on memristor neuromorphic device.

, , , , , , , , , and . ASICON, page 211-214. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 3D multi-layer CMOS-RRAM accelerator for neural network., , , , , , and . 3DIC, page 1-5. IEEE, (2016)OMI/TMI-based Modeling and Fast Simulation of Random Telegraph Noise (RTN) in Advanced Logic Devices and Circuits., , , , , , and . ASICON, page 1-4. IEEE, (2019)Realization of Nanoscale Neuromorphic Memristor Array with Low Power Consumption., , , , , , , and . ASICON, page 1-4. IEEE, (2019)Resistance switching for RRAM applications., , , , , , , , , and 4 other author(s). Sci. China Inf. Sci., 54 (5): 1073-1086 (2011)Neuromorphic Devices and Networks Based on Memristors with Ionic Dynamics., , and . Handbook of Memristor Networks, Springer, (2019)Challenges of 22 nm and beyond CMOS technology., , , , , , , , , and 1 other author(s). Sci. China Ser. F Inf. Sci., 52 (9): 1491-1533 (2009)DaSGD: Squeezing SGD Parallelization Performance in Distributed Training Using Delayed Averaging., , , , , , and . CoRR, (2020)Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life., , and . ICICDT, page 1-3. IEEE, (2016)Benchmarking TFET from a circuit level perspective: Applications and guideline., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method., , , , , and . ISCAS, page 1-4. IEEE, (2018)