( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique.

, , и . IEEE J. Solid State Circuits, 46 (6): 1360-1370 (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Thomas Mai

Carolin Mai

Konrad Mai

Erich Mai

Fritz Mai

 

Другие публикации лиц с тем же именем

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , и 2 other автор(ы). ISSCC, стр. 478-480. IEEE, (2019)A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver., , , , , , , , , и . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 107 (5): 709-718 (2024)A 10-bit, 40-MS/s, 1.21 mW Pipelined SAR ADC Using Single-Ended 1.5-bit/cycle Conversion Technique., , и . IEEE J. Solid State Circuits, 46 (6): 1360-1370 (2011)A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems., , , , , , , , , и 3 other автор(ы). IEEE J. Solid State Circuits, 57 (5): 1517-1526 (2022)A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR., , , , , , , , , и . ESSCIRC, стр. 505-508. IEEE, (2022)A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS., , и . ISSCC, стр. 382-383. IEEE, (2010)