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Disambiguation of "Miryala, Sandeep"

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Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications.

, , , , , , , , , , and . ISQED, page 1-6. IEEE, (2022)

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Sandeep Sadanandan

Sandeep Kumar

Sandeep Nambiar

Sandeep Ameta

Sandeep Pal

 

Other publications of authors with the same name

Exploration of different implementation styles for graphene-based reconfigurable gates., , , and . ICICDT, page 21-24. IEEE, (2013)Delay model for reconfigurable logic gates based on graphene PN-junctions., , , and . ACM Great Lakes Symposium on VLSI, page 227-232. ACM, (2013)A verilog-a model for reconfigurable logic gates based on graphene pn-junctions., , , , and . DATE, page 877-880. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch., , and . IET Circuits Devices Syst., 11 (6): 549-558 (2017)Ultra-low power circuits using graphene p-n junctions and adiabatic computing., , , , and . Microprocess. Microsystems, 39 (8): 962-972 (2015)Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array., , and . PRIME, page 113-116. IEEE, (2022)CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems.. Polytechnic University of Turin, Italy, (2014)An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies., , , and . ISQED, page 665-669. IEEE, (2013)A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (2): 123-133 (2022)Modeling of Physical Defects in PN Junction Based Graphene Devices., , , , , and . J. Electron. Test., 30 (3): 357-370 (2014)