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Disambiguation of "Hsieh, Chih-Cheng"

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A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors.

, , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 388-390. IEEE, (2019)

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Chih-Peng Hsieh

Chih-sheng Hsieh

Chih-Jen Hsieh

Chih-Cheng Jeng

Chih-Hong Cheng

 

Other publications of authors with the same name

Design of a 0.5 V 1.68mW nose-on-a-chip for rapid screen of chronic obstructive pulmonary disease., , , , , , , , , and 1 other author(s). BioCAS, page 592-595. IEEE, (2016)2.4-GHz 10-Mb/s BFSK Embedded Transmitter With a Stacked-LC DCO for Wireless Testing Systems., , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (9): 1727-1737 (2013)A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with semi-resting DAC., and . VLSI Circuits, page 1-2. IEEE, (2016)A High Performance Linear Current Mode Image Sensor., , and . ISCAS, page 1273-1276. IEEE, (2009)A CMOS time of flight (TOF) depth image sensor with in-pixel background cancellation and sensitivity improvement using phase shifting readout technique., , and . A-SSCC, page 133-136. IEEE, (2017)A 0.5V 4.95μW 11.8fps PWM CMOS imager with 82dB dynamic range and 0.055% fixed-pattern noise., and . ISSCC, page 114-116. IEEE, (2012)A 1.2V 1MS/s 7.65fJ/conversion-step 12-bit hybrid SAR ADC with time-to-digital converter., , and . ISCAS, page 2429-2432. IEEE, (2015)A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator., and . IEEE J. Solid State Circuits, 54 (6): 1648-1656 (2019)A Calibration-Free 13-Bit 10-MS/s Full-Analog SAR ADC With Continuous-Time Feedforward Cascaded Op-Amps., and . IEEE J. Solid State Circuits, 54 (10): 2691-2702 (2019)A 3 Megapixel 100 Fps 2.8 µm Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers., , and . IEEE J. Solid State Circuits, 48 (3): 839-849 (2013)