Author of the publication

A two-capacitor SAR-assisted multi-step incremental ADC with a single amplifier achieving 96.6 dB SNDR over 1.2 kHz BW.

, , , , , and . CICC, page 1-4. IEEE, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays., , , , , , , and . ESSCIRC, page 221-224. IEEE, (2015)A self-calibrated 2-1-1 cascaded continuous-time ΔΣ modulator., , , , and . CICC, page 9-12. IEEE, (2009)A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators., , , , , , , , , and . IEEE J. Solid State Circuits, 40 (12): 2398-2407 (2005)An Oversampling Stochastic ADC Using VCO-Based Quantizers., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4037-4050 (2018)A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity., , , , , and . IEEE J. Solid State Circuits, 49 (2): 416-425 (2014)A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR., , , , , , and . ISSCC, page 494-495. IEEE, (2008)A 16b 1.62MS/s Calibration-free SAR ADC with 86.6dB SNDR utilizing DAC Mismatch Cancellation Based on Symmetry., , , and . A-SSCC, page 1-2. IEEE, (2020)Parallel gain enhancement technique for switched-capacitor circuits., , , , , , and . CICC, page 1-4. IEEE, (2013)A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier., , , , , , , and . IEEE J. Solid State Circuits, 54 (12): 3410-3420 (2019)LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators., , , , and . IEEE J. Solid State Circuits, 45 (2): 368-379 (2010)