( en | de | ru )

 

Disambiguation of "Seiculescu, Ciprian"

Author of the publication

copydeleteadd this publication to your clipboard
Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.

, , , and . Low Power Networks-on-Chip, Springer, (2011)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jürgen Ciprian

Ciprian Neagoe

Ciprian Zafiu

Ciprian Roman

Jürgen Ciprian

 

Other publications of authors with the same name

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks., , , and . 3D Integration for NoC-based SoC Architectures, Springer, (2011)SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (12): 1987-2000 (2010)3.5-D integration: A case study., , , , and . ISCAS, page 2087-2090. IEEE, (2013)Benchmarking TensorFlow Lite Quantization Algorithms for Deep Neural Networks., , and . SACI, page 221-226. IEEE, (2022)A DRAM Centric NoC Architecture and Topology Design Approach., , , and . ISVLSI, page 54-59. IEEE Computer Society, (2011)Synthesis of networks on chips for 3D systems on chips., , , and . ASP-DAC, page 242-247. IEEE, (2009)Networks on Chips: from research to products., , , , , and . DAC, page 300-305. ACM, (2010)Design and Analysis of NoCs for Low-Power 2D and 3D SoCs., , , and . Low Power Networks-on-Chip, Springer, (2011)Design Methods and Tools for Application-Specific Predictable Networks-on-Chip.. EPFL, Switzerland, (2012)A floorplan-aware interactive tool flow for NoC design and synthesis., , , , , and . SoCC, page 379-382. IEEE, (2009)