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A leakage-tolerant low-leakage register file with conditional sleep transistor., , и . SoCC, стр. 241-244. IEEE, (2004)Exploring the design space of mixed swing quadrail for low-power digital circuits., и . IEEE Trans. Very Large Scale Integr. Syst., 5 (4): 388-400 (1997)Energy efficient and ultra low voltage security circuits for nanoscale CMOS technologies., , , и . CICC, стр. 1-4. IEEE, (2017)A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition., , , , , , , , , и 2 other автор(ы). IEEE J. Solid State Circuits, 55 (4): 945-955 (2020)A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS., , , , , и . IEEE J. Solid State Circuits, 40 (1): 44-51 (2005)microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware., , , , , и . ESSCIRC, стр. 421-424. IEEE, (2023)A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS., , , , и . ESSCIRC, стр. 316-319. IEEE, (2007)High-performance and low-power challenges for sub-70 nm microprocessor circuits., , , и . CICC, стр. 125-128. IEEE, (2002)16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS., , , , , , , , , и . ISSCC, стр. 276-277. IEEE, (2014)A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS., , , , , , , , , и 1 other автор(ы). VLSI Circuits, стр. 1-2. IEEE, (2020)