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A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain-Error-Shaping and NS Pipelined SAR ADC Based on a Quantization-Prediction-Unrolled Scheme., , , and . ISSCC, page 174-175. IEEE, (2023)A 10-Bit 200-kS/s 1.76- $\mu$ W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (5): 1716-1727 (2019)A Second-Order NS Pipelined SAR ADC With Quantization-Prediction-Unrolled Gain Error Shaping and Fully Passive Integrator., , , and . IEEE J. Solid State Circuits, 58 (12): 3565-3575 (December 2023)A 10-bit 200-kS/s 1.76-μW SAR ADC with Hybrid CAP-MOS DAC for Energy-Limited Applications., , , and . ISCAS, page 1-5. IEEE, (2018)A Nano-Watt MOS-Only Voltage Reference With High-Slope PTAT Voltage Generators., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (1): 1-5 (2018)An Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC With Code-Counter-Based Offset Calibration., , , and . IEEE J. Solid State Circuits, 57 (5): 1480-1491 (2022)Bi-LSTM-Based Dynamic Prediction Model for Pulling Speed of Czochralski Single-Crystal Furnace., , , , , and . J. Comput. Inf. Sci. Eng., (August 2023)3D Model Registration-Based Batch Wafer-ID Recognition Algorithm., , , , , and . IEEE Access, (2021)27.6 A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration., , , and . ISSCC, page 380-382. IEEE, (2021)