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Design Space Exploration of Memory Controller Placement in Throughput Processors with Deep Learning.

, , , and . IEEE Comput. Archit. Lett., 18 (1): 51-54 (2019)

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CALM: Contention-Aware Latency-Minimal Application Mapping for Flattened Butterfly On-Chip Networks., , , and . ACM Trans. Design Autom. Electr. Syst., 22 (2): 21:1-21:21 (2017)Bubble coloring: avoiding routing- and protocol-induced deadlocks with minimal virtual channel requirement., , and . ICS, page 193-202. ACM, (2013)Simulation of NoC power-gating: Requirements, optimizations, and the Agate simulator., , , and . J. Parallel Distributed Comput., (2016)A comparative study for solution methods of a multicomponent distillation model., , , and . SMC (5), page 4249-4253. IEEE, (2004)The gem5 Simulator: Version 20.0+., , , , , , , , , and 63 other author(s). CoRR, (2020)Implicit Memory Transformer for Computationally Efficient Simultaneous Speech Translation., and . ACL (Findings), page 12900-12907. Association for Computational Linguistics, (2023)Worm-Bubble Flow Control., and . HPCA, page 366-377. IEEE Computer Society, (2013)Power punch: Towards non-blocking power-gating of NoC routers., , , and . HPCA, page 378-389. IEEE Computer Society, (2015)Express Link Placement for NoC-Based Many-Core Platforms., , and . ICPP, page 27:1-27:10. ACM, (2019)Maximizing the performance of NoC-based MPSoCs under total power and power density constraints., , , , and . ISQED, page 49-56. IEEE, (2016)