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A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF.

, , , , and . IEEE Access, (2020)

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A 8800 μm² CCO-Based Voltage-Droop and Temperature Detector in 65 nm., , and . IEEE Access, (2021)A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF., , , , and . IEEE Access, (2020)MirrorN PUF: Harvesting Multiple Independent Bits From Each PUF Cell in 65nm., , and . ISCAS, page 2418-2422. IEEE, (2022)An SRAM PUF with 2 Independent Bits/Cell in 65nm., , , , and . ISCAS, page 1-5. IEEE, (2019)Preselection Methods to Achieve Very Low BER in SRAM-Based PUFs - A Tutorial., and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2551-2556 (2022)A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic., , , , , and . IEEE J. Solid State Circuits, 57 (2): 596-608 (2022)A Highly Reliable SRAM PUF with a Capacitive Preselection Mechanism and pre-ECC BER of 7.4E-10., , , , and . CICC, page 1-4. IEEE, (2019)112-Gb/s PAM4 ADC-Based SERDES Receiver With Resonant AFE for Long-Reach Channels., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 55 (4): 1077-1085 (2020)A 1.64mW Differential Super Source-Follower Buffer with 9.7GHz BW and 43dB PSRR for Time-Interleaved ADC Applications in 10nm., , , , , and . A-SSCC, page 235-238. IEEE, (2019)A 2 Bit/Cell Tilting SRAM-Based PUF With a BER of 3.1E-10 and an Energy of 21 FJ/Bit in 65nm., , , and . IEEE Open J. Circuits Syst., (2020)