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DIAN: Differentiable Accelerator-Network Co-Search Towards Maximal DNN Efficiency.

, , , , , , , and . ISLPED, page 1-6. IEEE, (2021)

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Energy-Aware Neural Architecture Optimization with Fast Splitting Steepest Descent., , , , and . CoRR, (2019)Analytical model for TDDB-based performance degradation in combinational logic., , , and . DATE, page 423-428. IEEE Computer Society, (2010)A black box method for stability analysis of arbitrary SRAM cell structures., , , , , , and . DATE, page 795-800. IEEE Computer Society, (2010)Impact of voltage scaling on nanoscale SRAM reliability., and . DATE, page 387-392. IEEE, (2009)Leveraging sensitivity analysis for fast, accurate estimation of SRAM dynamic write VMIN., , , and . DATE, page 1819-1824. EDA Consortium San Jose, CA, USA / ACM DL, (2013)TIMBER: Time borrowing and error relaying for online timing error resilience., , , and . DATE, page 1554-1559. IEEE Computer Society, (2010)Modeling SRAM dynamic VMIN., , , and . ICICDT, page 1-4. IEEE, (2014)Not All Ops Are Created Equal!, , and . CoRR, (2018)Variation-aware static and dynamic writability analysis for voltage-scaled bit-interleaved 8-T SRAMs., , , , and . ISLPED, page 145-150. IEEE/ACM, (2011)A digital dynamic write margin sensor for low power read/write operations in 28nm SRAM., , , and . ISLPED, page 307-310. ACM, (2014)