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CaSym: Cache Aware Symbolic Execution for Side Channel Detection and Mitigation.

, , , , and . IEEE Symposium on Security and Privacy, page 505-521. IEEE, (2019)

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Compilation for Distributed Memory Architectures., and . The Compiler Design Handbook, CRC Press, (2002)Adaptive prefetching for shared cache based chip multiprocessors., , and . DATE, page 773-778. IEEE, (2009)Performance aware secure code partitioning., , and . DATE, page 1122-1127. EDA Consortium, San Jose, CA, USA, (2007)Memory bank aware dynamic loop scheduling., , , and . DATE, page 1671-1676. EDA Consortium, San Jose, CA, USA, (2007)FUSE: Fusing STT-MRAM into GPUs to Alleviate Off-Chip Memory Access Overheads., , and . HPCA, page 426-439. IEEE, (2019)Leveraging value locality for efficient design of a hybrid cache in multicore processors., , , and . ICCAD, page 1-8. IEEE, (2017)Using data replication to reduce communication energy on chip multiprocessors., , , and . ASP-DAC, page 769-772. ACM Press, (2005)Optimizing embedded applications using programmer-inserted hints., and . ASP-DAC, page 157-160. ACM Press, (2005)The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense., , , , , and . IJDSN, 2 (3): 267-287 (2006)Architecture-Centric Bottleneck Analysis for Deep Neural Network Applications., , , , , , and . HiPC, page 205-214. IEEE, (2019)