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Interlaced asymmetric search range assignment for bidirectional motion estimation., , and . ICIP, page 1557-1560. IEEE, (2012)An area-efficient 4/8/16/32-point inverse DCT architecture for UHDTV HEVC decoder., , , , and . VCIP, page 197-200. IEEE, (2014)A High Performance and Low Bandwidth Multi-Standard Motion Compensation Design for HD Video Decoder., , , , , and . IEICE Trans. Electron., 93-C (3): 253-260 (2010)A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2612-2622 (2013)Low-Power Motion Estimation Processor with 3D Stacked Memory., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 98-A (7): 1431-1441 (2015)The Switching Glitch Power Leakage Model., , , and . J. Softw., 6 (9): 1787-1794 (2011)HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis., , , , , , , , and . IEEE J. Solid State Circuits, 44 (2): 594-608 (2009)Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC., , and . J. Vis. Commun. Image Represent., 25 (5): 1275-1286 (2014)An independent bandwidth reduction device for HEVC VLSI video system., , , , and . ISCAS, page 609-612. IEEE, (2015)Hardware-Oriented Early Detection Algorithms for 4×4 and 8×8 All-Zero Blocks in H.264, , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (4): 1063-1071 (2009)