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Disambiguation of "Tomita, Yasumoto"

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A Dynamic Offset Control Technique for Comparator Design in Scaled CMOS Technology.

, , , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (12): 2456-2462 (2010)

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Takemasa Tomita

Naoko Tomita

Yuto Tomita

 

Other publications of authors with the same name

GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning., , , , and . Int. J. Netw. Comput., 8 (2): 408-433 (2018)An FPGA-accelerated partial image matching engine for massive media data searching systems., , , , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)An FPGA-accelerated partial duplicate image retrieval engine for a document search system., , , , , and . WACV, page 1-7. IEEE Computer Society, (2016)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 45 (10): 2016-2029 (2010)Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC., , , , , , , , , and 2 other author(s). IEICE Trans. Electron., 93-C (3): 295-302 (2010)Speed-Up of Object Detection Neural Network with GPU., , , , , , and . ICIP, page 301-305. IEEE, (2018)GUNREAL: GPU-accelerated UNsupervised REinforcement and Auxiliary Learning., , , , and . CANDAR, page 330-336. IEEE Computer Society, (2017)A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid., , , , , and . ISSCC, page 2102-2111. IEEE, (2006)What is a good way to expand a silicon value to a solution value?, , , , , , , , , and 1 other author(s). A-SSCC, page 389-394. IEEE, (2014)A combined anti-aliasing filter and 2-tap FFE in 65-nm CMOS for 2× blind 2-;10 Gb/s ADC-based receivers., , , , , and . CICC, page 1-4. IEEE, (2010)