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Intel Alder Lake CPU Architectures., , , , , , , , , и 2 other автор(ы). IEEE Micro, 42 (3): 13-19 (2022)Correlated Load-Address Predictors., , , , , , и . ISCA, стр. 54-63. IEEE Computer Society, (1999)Inside 6th gen Intel® Core™: New microarchitecture code named skylake., , , , , , , , и . Hot Chips Symposium, стр. 1-39. IEEE, (2016)Disjoint-Access-Parallel Implementations of Strong Shared Memory Primitives., и . PODC, стр. 151-160. ACM, (1994)Inside 6th-Generation Intel Core: New Microarchitecture Code-Named Skylake., , , , , , , , и . IEEE Micro, 37 (2): 52-62 (2017)On the Robustness of h^r_m., и . WDAG, том 1151 из Lecture Notes in Computer Science, стр. 344-361. Springer, (1996)Lock-Free implementations in the asynchronous shared-memory model.. Technion - Israel Institute of Technology, Israel, (1996)eXtended Block Cache., , , , , и . HPCA, стр. 61-70. IEEE Computer Society, (2000)Towards the adoption of Local Branch Predictors in Modern Out-of-Order Superscalar Processors., , , , , , , , и . MICRO, стр. 519-530. ACM, (2019)Efficient Wait-Free Implementation of a Concurrent Priority Queue., и . WDAG, том 725 из Lecture Notes in Computer Science, стр. 1-17. Springer, (1993)