( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Floorplan Design for Multimillion Gate FPGAs.

, и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (12): 2795-2805 (2006)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Alexander D F Lahmann

Blaise F D Bourgeois

Walter Wong

Martin F Almstetter

Martin F Polaschek

 

Другие публикации лиц с тем же именем

Layout Decomposition for Multiple Patterning., и . Encyclopedia of Algorithms, (2016)Circuit clustering for delay minimization under area and pin constraints., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (9): 976-986 (1997)Dummy-feature placement for chemical-mechanical polishinguniformity in a shallow-trench isolation process., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 63-71 (2002)On shifting blocks and terminals to minimize channel density., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 13 (2): 178-186 (1994)Fast Dummy-Fill Density Analysis With Coupling Constraints., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (4): 633-642 (2008)Maze routing with buffer insertion and wiresizing., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (10): 1205-1209 (2002)Hinted quad trees for VLSI geometry DRC based on efficient searching for neighbors., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (3): 317-324 (1996)CTM-SRAF: Continuous Transmission Mask-Based Constraint-Aware Subresolution Assist Feature Generation., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (10): 3402-3411 (октября 2023)GAMER: GPU-Accelerated Maze Routing., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 583-593 (февраля 2023)PolyPUF: Physically Secure Self-Divergence., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (7): 1053-1066 (2016)