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Disambiguation of "Wang, Chorng-Kuang"

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A low power high reliability dual-path noise-cancelling LNA for WSN applications.

, , and . CICC, page 1-4. IEEE, (2010)

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Pei Kuang

Peng Kuang

Xutao Kuang

Zhanghui Kuang

Zheng-Zheng Kuang

 

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A 1V 19.3dBm 79GHz power amplifier in 65nm CMOS., , and . ISSCC, page 260-262. IEEE, (2012)Joint Carrier Synchronization and Equalization Algorithm for Packet-Based OFDM Systems Over the Multipath Fading Channel., , and . IEEE Trans. Vehicular Technology, 59 (1): 248-260 (2010)A 4.9-mW 4-Gb/s single-to-differential TIA with current-amplifying regulated cascode., , , and . VLSI-DAT, page 1-4. IEEE, (2012)A CMOS Cantilever-Based Label-Free DNA SoC With Improved Sensitivity for Hepatitis B Virus Detection., , , , , , , , , and 4 other author(s). IEEE Trans. Biomed. Circuits Syst., 7 (6): 820-831 (2013)Joint Carrier Synchronization and Equalization Algorithm for OFDM Systems - Closed-Loop Derivation., , and . VTC Spring, IEEE, (2009)A fully integrated hepatitis B virus DNA detection SoC based on monolithic polysilicon nanowire CMOS process., , , , , , , , , and 4 other author(s). VLSIC, page 124-125. IEEE, (2012)A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier., , , , and . ISCAS (4), page 393-396. IEEE, (2004)A 90 nm CMOS V-Band Low-Noise Active Balun With Broadband Phase-Correction Technique., , , and . IEEE J. Solid State Circuits, 46 (11): 2583-2591 (2011)A 1V 10-bit 500KS/s energy-efficient SAR ADC using Master-Slave DAC technique in 180nm CMOS., , and . VLSI-DAT, page 1-4. IEEE, (2014)A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator., and . ESSCIRC, page 375-378. IEEE, (2004)