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Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test.

, , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (5): 818-830 (2018)

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A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)., и . IEEE Trans. Very Large Scale Integr. Syst., 14 (11): 1216-1226 (2006)Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test., , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (5): 818-830 (2018)A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging., , , и . J. Electron. Test., 33 (6): 721-739 (2017)Extending integrated-circuit yield-models to estimate early-life reliability., , и . IEEE Trans. Reliability, 52 (3): 296-300 (2003)A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI., и . ICPP (1), стр. 261-265. Pennsylvania State University Press, (1989)A differential built-in current sensor design for high-speed IDDQ testing., и . IEEE J. Solid State Circuits, 32 (1): 122-125 (1997)Low-power domino circuits using NMOS pull-up on off-critical paths., , , и . ASP-DAC, стр. 533-538. ACM Press, (2005)On the Effect of Defect Clustering on Test Transparency and IC Test Optimization., и . IEEE Trans. Computers, 45 (6): 753-757 (1996)Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules., , и . IEEE Trans. Computers, 30 (9): 671-674 (1981)On optimizing VLSI testing for product quality using die-yield prediction., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (5): 695-709 (1993)