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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.

A. Cassidy, J. Arthur, F. Akopyan, A. Andreopoulos, R. Appuswamy, P. Datta, M. DeBole, S. Esser, C. Otero, J. Sawada, B. Taba, A. Amir, D. Bablani, P. Carlson, M. Flickner, R. Gandhasri, G. Garreau, M. Ito, J. Klamo, J. Kusnitz, N. McClatchey, J. McKinstry, Y. Nakamura, T. Nayak, W. Risk, K. Schleupen, B. Shaw, J. Sivagnaname, D. Smith, I. Terrizzano, T. Ueda, and D. Modha. ISSCC, page 214-215. IEEE, (2024)

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Steven Liu

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A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons.J. sun Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha and 1 other author(s). CICC, page 1-4. IEEE, (2011)Low Precision Policy Distillation with Application to Low-Power, Real-time Sensation-Cognition-Action Loop with Neuromorphic Computing.J. McKinstry, D. Barch, D. Bablani, M. DeBole, S. Esser, J. Kusnitz, J. Arthur, and D. Modha. CoRR, (2018)Cognitive computing.D. Modha, R. Ananthanarayanan, S. Esser, A. Ndirango, A. Sherbondy, and R. Singh. Commun. ACM, 54 (8): 62-71 (2011)Efficient and Effective Methods for Mixed Precision Neural Network Quantization for Faster, Energy-efficient Inference.D. Bablani, J. McKinstry, S. Esser, R. Appuswamy, and D. Modha. CoRR, (2023)Cognitive computing building block: A versatile and efficient digital neuron model for neurosynaptic cores.A. Cassidy, P. Merolla, J. Arthur, S. Esser, B. Jackson, R. Alvarez-Icaza, P. Datta, J. Sawada, T. Wong, V. Feldman and 6 other author(s). IJCNN, page 1-10. IEEE, (2013)A Low Power, Fully Event-Based Gesture Recognition System.A. Amir, B. Taba, D. Berg, T. Melano, J. McKinstry, C. di Nolfo, T. Nayak, A. Andreopoulos, G. Garreau, M. Mendoza and 6 other author(s). CVPR, page 7388-7397. IEEE Computer Society, (2017)Binding sparse spatiotemporal patterns in spiking computation.S. Esser, A. Ndirango, and D. Modha. IJCNN, page 1-9. IEEE, (2010)Learned Step Size Quantization.S. Esser, J. McKinstry, D. Bablani, R. Appuswamy, and D. Modha. CoRR, (2019)Truenorth ecosystem for brain-inspired computing: scalable systems, software, and applications.J. Sawada, F. Akopyan, A. Cassidy, B. Taba, M. DeBole, P. Datta, R. Alvarez-Icaza, A. Amir, J. Arthur, A. Andreopoulos and 36 other author(s). SC, page 130-141. IEEE Computer Society, (2016)IBM NorthPole Neural Inference Machine.D. Modha, F. Akopyan, A. Andreopoulos, R. Appuswamy, J. Arthur, A. Cassidy, P. Datta, M. DeBole, S. Esser, C. Otero and 22 other author(s). HCS, page 1-58. IEEE, (2023)

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Disambiguation of "Esser, Steven K."

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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.

Please choose a person to relate this publication to

Steven Liu

Steven Ding

Adolf Steven

Steven Ahlig

Doris Steven

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Esser, Steven K."

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML 11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.

Please choose a person to relate this publication to

Steven Liu

Steven Ding

Adolf Steven

Steven Ahlig

Doris Steven

Other publications of authors with the same name

Disambiguation

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11.4 IBM NorthPole: An Architecture for Neural Network Inference with a 12nm Chip.