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Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation.

, , , , , and . IEEE Trans. Dependable Secur. Comput., 8 (5): 756-769 (2011)

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Low-energy digital filter design based on controlled timing error acceptance., , and . ISQED, page 151-157. IEEE, (2013)Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems., , and . IEEE Trans. Circuits Syst. Video Techn., 23 (6): 961-974 (2013)Temperature-aware NBTI modeling and the impact of input vector control on performance degradation., , , , , and . DATE, page 546-551. EDA Consortium, San Jose, CA, USA, (2007)Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (9): 1101-1113 (2008)Controlled timing-error acceptance for low energy IDCT design., , and . DATE, page 758-763. IEEE, (2011)A power gating scheme for ground bounce reduction during mode transition., , and . ICCD, page 388-394. IEEE, (2007)Low-energy signal processing using circuit-level timing-error acceptance., , and . ICICDT, page 1-4. IEEE, (2012)Modeling and synthesis of quality-energy optimal approximate adders., , , and . ICCAD, page 728-735. ACM, (2012)A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect., , , , , and . PATMOS, volume 4644 of Lecture Notes in Computer Science, page 160-170. Springer, (2007)Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation., , , , , and . IEEE Trans. Dependable Secur. Comput., 8 (5): 756-769 (2011)