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25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM.

, , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , and . ISSCC, page 346-348. IEEE, (2021)

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