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Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs.

, , , , and . J. Parallel Distributed Comput., (2016)

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Hardware support for early register release., , , and . IJHPCN, 3 (2/3): 83-94 (2005)Characterization and Improvement of Load/Store Cache-based Prefetching., , , and . International Conference on Supercomputing, page 369-376. ACM, (1998)Speeding-Up Synchronizations in DSM Multiprocessors., , , , and . Euro-Par, volume 4128 of Lecture Notes in Computer Science, page 473-484. Springer, (2006)Counteracting Bank Misprediction in Sliced First-Level Caches., , , and . Euro-Par, volume 2790 of Lecture Notes in Computer Science, page 586-596. Springer, (2003)Forecasting lifetime and performance of a novel NVM last-level cache with compression., , , , and . CoRR, (2022)Characterization and cost-efficient selection of NoC topologies for general purpose CMPs., , , , , , and . INA-OCMC@HiPEAC, page 21-24. ACM, (2013)Multi-level Adaptive Prefetching based on Performance Gradient Tracking., , , and . J. Instruction-Level Parallelism, (2011)Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors., , , , , and . HPCA, page 191-202. IEEE Computer Society, (2003)Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding., , , , , and . DCC, page 577. IEEE, (2019)Speculative early register release., , , and . Conf. Computing Frontiers, page 291-302. ACM, (2006)