( en | de | ru )

 

Disambiguation of "Chen, Tianzhou"

Author of the publication

copydeleteadd this publication to your clipboard
Global Register Alias Table: Executing Sequential Program on Multi-Core.

, , , , , and . CIT, page 1818-1824. IEEE Computer Society, (2010)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Tianzhou He

Chen Chen

Chen Chen

Shih Chen Chen

Yi-Chen Chen

 

Other publications of authors with the same name

Global register alias table: Boosting sequential program on multi-core., , , and . Future Gener. Comput. Syst., 28 (6): 957-964 (2012)A reconfigurable processor architecture combining multi-core and reconfigurable processing units., , , , and . Telecommun. Syst., 55 (3): 333-344 (2014)Potential thread-level-parallelism exploration with superblock reordering., , , and . Computing, 96 (6): 545-564 (2014)The Modeling for Dynamic Power Management of Embedded Systems., , , and . ICESS, volume 3605 of Lecture Notes in Computer Science, page 462-467. Springer, (2004)Battery-aware task scheduling in distributed mobile systems with lifetime constraint., , , and . ASP-DAC, page 743-748. IEEE, (2011)A Selective Read-before-Write Scheme for Energy-Aware Spin Torque Transfer RAM (STT-RAM) Cache Design., , , and . Journal of Circuits, Systems, and Computers, (2013)Regional cache organization for NoC based many-core processors., , , and . J. Comput. Syst. Sci., 79 (2): 175-186 (2013)Shared write buffer to boost applications on SpMT architecture., , , and . J. Supercomput., 73 (8): 3508-3525 (2017)Critical-Path Driven Routers for on-Chip Networks., , , and . Journal of Circuits, Systems, and Computers, 19 (7): 1543-1557 (2010)Embedded hard real-time scheduling algorithm based on task's resource requirement., , , and . IJHPCN, 6 (3/4): 234-239 (2010)