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Path-Balanced Logic Design to Realize Block Ciphers Resistant to Power and Timing Attacks.

, , и . IEEE Trans. Very Large Scale Integr. Syst., 27 (5): 1080-1092 (2019)

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Sumesh Udayakumaran

Andreyasa Udayana

Udaya K Tiruttani Subhramanyam

Karumpullige Udaya Thilaka Gunasekara

 

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