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A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links.

, , , , , , and . IEEE J. Solid State Circuits, 54 (11): 3180-3190 (2019)

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A fully-integrated 10.5 to 13.5 Gbps transceiver in 0.13 μm CMOS., , , , and . CICC, page 595-598. IEEE, (2003)A process and temperature insensitive CMOS linear TIA for 100 Gbps/λ PAM-4 optical links., , , , and . CICC, page 1-4. IEEE, (2018)An Interference Suppression Technique for Millimeter-Wave LC VCOs Using a Multiport Coupled Inductor., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 919-923 (2022)Analog PLL Design With Ring Oscillators at Low-Gigahertz Frequencies in Nanometer CMOS: Challenges and Solutions.. IEEE Trans. Circuits Syst. II Express Briefs, 56-II (5): 389-393 (2009)A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links., , , , , , and . IEEE J. Solid State Circuits, 54 (11): 3180-3190 (2019)A 7 pA/$\surdHz$ Asymmetric Differential TIA for 100Gb/s PAM-4 links with -14dBm Optical Sensitivity in 16nm CMOS., , , , , , and . ISSCC, page 206-207. IEEE, (2023)A low-power 0.13μm CMOS OC-48 SONET and XAUI compliant SERDES., , , , , , , and . CICC, page 577-580. IEEE, (2003)A Process and Temperature Compensated Two-Stage Ring Oscillator., , and . CICC, page 691-694. IEEE, (2007)A CMOS self-calibrating frequency synthesizer., , , and . IEEE J. Solid State Circuits, 35 (10): 1437-1444 (2000)A baseband processor for IS-54 cellular telephony., , , , and . IEEE J. Solid State Circuits, 31 (5): 646-655 (1996)