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Disambiguation of "Nakahara, Hiroki"

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A regular expression matching circuit: Decomposed non-deterministic realization with prefix sharing and multi-character transition.

, , and . Microprocess. Microsystems, 36 (8): 644-664 (2012)

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Hiroki Takahashi

Hiroki Kawamura

Yasuji Nakahara

Hiroki Sumizawa

 

Other publications of authors with the same name

FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network., , , , , and . FPL, page 180-186. IEEE, (2019)An Update Method for a Low Power Cam Emulator Using an LUT Cascade Based on an EVMDD (k)., , , and . J. Multiple Valued Log. Soft Comput., 26 (1-2): 109-123 (2016)A Quaternary Decision Diagram Machine: Optimization of Its Code., , , , and . IEICE Trans. Inf. Syst., 93-D (8): 2026-2035 (2010)A Threshold Neuron Pruning for a Binarized Deep Neural Network on an FPGA., , and . IEICE Trans. Inf. Syst., 101-D (2): 376-386 (2018)An AWF digital spectrometer for a radio telescope., , and . ReConFig, page 1-6. IEEE, (2014)A fully connected layer elimination for a binarizec convolutional neural network on an FPGA., , and . FPL, page 1-4. IEEE, (2017)A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA., , , and . FPT, page 267-270. IEEE, (2019)An FPGA Realization of OpenPose Based on a Sparse Weight Convolutional Neural Network., , , and . FPT, page 310-313. IEEE, (2018)Multilayer Perceptron Training Accelerator Using Systolic Array., , , and . IEICE Trans. Inf. Syst., 105-D (12): 2048-2056 (December 2022)FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling., , and . J. Signal Process. Syst., 93 (5): 499-512 (2021)