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A Novel ATPG Method for Capture Power Reduction during Scan Testing., , , , , , and . IEICE Trans. Inf. Syst., 90-D (9): 1398-1405 (2007)Turbo1500: Core-Based Design for Test and Diagnosis., , , , , , , , , and 5 other author(s). IEEE Des. Test Comput., 26 (1): 26-35 (2009)Self-Testing of Embedded RAMs., and . ITC, page 148-156. IEEE Computer Society, (1984)Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing., , and . ACM Trans. Design Autom. Electr. Syst., 17 (2): 18:1-18:24 (2012)Low-capture-power test generation for scan-based at-speed testing., , , , , , and . ITC, page 10. IEEE Computer Society, (2005)At-Speed Logic BIST for IP Cores., , , , , , , , and . DATE, page 860-861. IEEE Computer Society, (2005)CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing., , , , , , , and . ATS, page 397-402. IEEE Computer Society, (2008)VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG., , , , , , and . IEEE Des. Test Comput., 25 (2): 122-130 (2008)Testing of Synchronizers in Asynchronous FIFO., , , and . J. Electron. Test., 29 (1): 49-72 (2013)CPP-ATPG: A Circular Pipeline Processing Based Deterministic Parallel Test Pattern Generator., , and . J. Electron. Test., 32 (5): 625-638 (2016)