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Другие публикации лиц с тем же именем

On-Chip Delay Measurement for In-Field Test of FPGAs., , и . PRDC, стр. 130-137. IEEE, (2019)Scan-Out Power Reduction for Logic BIST., , , и . IEICE Trans. Inf. Syst., 96-D (9): 2012-2020 (2013)Not all Delay Tests Are the Same - SDQL Model Shows True-Time., , , , , и . ATS, стр. 147-152. IEEE, (2006)Good Die Prediction Modelling from Limited Test Items., , , и . ITC-Asia, стр. 115-120. IEEE, (2018)An evaluation of defect-oriented test: WELL-controlled low voltage test., , , , и . ITC, стр. 1059-1067. IEEE Computer Society, (2001)An Approach to Improve the Resolution of Defect-Based Diagnosis., , , , и . Asian Test Symposium, стр. 123-. IEEE Computer Society, (2001)On Achieving Capture Power Safety in At-Speed Scan-Based Logic BIST., , , , , , и . Asian Test Symposium, стр. 19-24. IEEE Computer Society, (2013)An On-Chip Digital Environment Monitor for Field Test., , , и . ATS, стр. 254-257. IEEE Computer Society, (2014)A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST., , , , и . ATS, стр. 203-208. IEEE Computer Society, (2016)Effective Post-BIST Fault Diagnosis for Multiple Faults., , , , , , и . DFT, стр. 401-109. IEEE Computer Society, (2006)