( en | de | ru )

 

Disambiguation of "Raghunathan, Anand"

Author of the publication

copydeleteadd this publication to your clipboard
Compute-in-Memory Technologies and Architectures for Deep Learning Workloads.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (11): 1615-1630 (2022)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Davinder Kumar Anand

Raghunathan Ramakrishnan

Devanathan Raghunathan

Amar Frank Anand

Madhankumar Anandhakrishnan

 

Other publications of authors with the same name

Hardware Accelerated Power Estimation, , and . CoRR, (2007)High-level macro-modeling and estimation techniques for switching activity and power consumption., , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (4): 538-557 (2003)Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems., , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (3): 296-308 (2007)Variation-Aware System-Level Power Analysis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1173-1184 (2010)Emulation-Based Analysis of System-on-Chip Performance Under Variations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (12): 3401-3414 (2016)Generation of distributed logic-memory architectures through high-level synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 24 (11): 1694-1711 (2005)Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2193-2206 (2006)High-level energy macromodeling of embedded software., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (9): 1037-1050 (2002)Design space exploration for optimizing on-chip communication architectures., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (6): 952-961 (2004)Application-specific heterogeneous multiprocessor synthesis using extensible processors., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1589-1602 (2006)