Author of the publication

A wideband sub-6GHz continuously tunable gm-boosted CG Low Noise Amplifier in 28 nm FD-SOI CMOS technology.

, , , and . ESSCIRC, page 381-384. IEEE, (2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge"., , , , , , , , and . IEEE Access, (2023)Guest Editorial: Analog, Mixed-Signal and RF Testing., and . J. Electron. Test., 33 (3): 281-282 (2017)A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs., , , , , , and . J. Electron. Test., 32 (4): 407-421 (2016)A harmonic cancellation-based high-frequency on-chip sinusoidal signal generator with calibration using a coarse-fine delay cell., , , and . ISCAS, page 1-5. IEEE, (2023)A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology., , and . VLSI-SoC, page 1-6. IEEE, (2022)A 5-DC-parameter MOSFET model for circuit simulation in QucsStudio and SPECTRE., , , , , , , , and . NEWCAS, page 1-5. IEEE, (2023)mm-Wave Single-Pole Double-Throw switches: HBT- vs MOSFET-based designs., , , , , , , and . NEWCAS, page 1-4. IEEE, (2021)Sinusoidal signal generation for mixed-signal BIST using a harmonic-cancellation technique., , , and . LASCAS, page 1-4. IEEE, (2013)Innovative Practices Track: Innovative Analog Circuit Testing Technologies., , , , , , , , , and 8 other author(s). VTS, page 1. IEEE, (2022)A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System., , , , , , , , , and 1 other author(s). IOLTS, page 1-4. IEEE, (2020)