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An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization.

, , , and . GECCO, page 1232-1239. ACM, (2017)

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Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction., , , and . Int. J. Softw. Tools Technol. Transf., 21 (5): 545-565 (2019)RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms., , and . ATVA, volume 12302 of Lecture Notes in Computer Science, page 543-549. Springer, (2020)Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents., , , , and . DSD, page 129-136. IEEE, (2019)Functional Coverage-Driven Characterization of RF Amplifiers., , , , and . FDL, page 1-8. IEEE, (2019)Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm., , , and . GECCO (Companion), page 79-80. ACM, (2016)From Requirements and Scenarios to ESL Design in SystemC., , and . ISED, page 183-187. IEEE, (2012)Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime., , , and . ICCD, page 312-315. IEEE, (2020)Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability., , , , and . DAC, page 1183-1188. ACM, (2022)RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers., , and . DAC, page 185. ACM, (2019)Formal Verification of SUBLEQ Microcode implementing the RV32I ISA., , and . FDL, page 1-8. IEEE, (2022)