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Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes., , , , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 29 (4): 677-690 (2021)On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification., , , , , и . DFT, стр. 1-6. IEEE, (2019)Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features., , , , , и . EUSIPCO, стр. 1690-1694. IEEE, (2018)Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores., , , , , и . ISCAS, стр. 1-5. IEEE, (2021)Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node., , , , и . CoRR, (2020)Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA., , , , , , и . CoRR, (2024)Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition., , , , , и . SYSINT, том 546 из Lecture Notes in Networks and Systems, стр. 518-529. Springer, (2022)X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators., , , , и . CoRR, (2024)An evolutionary approach for test program compaction., , , , и . LATS, стр. 1-6. IEEE Computer Society, (2015)Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces., , , , , , , и . AICAS, стр. 50-54. IEEE, (2020)