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Radiation sensitivity of XOR topologies in multigate technologies under voltage variability., , and . LASCAS, page 1-4. IEEE, (2017)Comparing 32nm full adder TMR and DTMR architectures., , and . ICECS, page 294-297. IEEE, (2017)orBDDs Direct Mapping for Structured Logic Circuits., , and . ICECS, page 1057-1060. IEEE, (2006)Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology., , , , and . Integr., (2022)Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs., , , , , and . VLSI-SoC, page 240-241. IEEE, (2019)Evaluation of variability using Schmitt trigger on full adders layout., , , and . Microelectron. Reliab., (2018)Recovery scheme for hardening system on programmable chips., , , and . LATW, page 1-6. IEEE, (2009)Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study., , , , , and . LATS, page 1-6. IEEE, (2021)Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters., , , and . LATS, page 1-6. IEEE, (2020)A Detailed Electrical Analysis of SEE on 28 nm FDSOI SRAM Architectures., , , , , , and . SBCCI, page 1-6. IEEE, (2023)