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The Next 700 Accelerated Layers: From Mathematical Expressions of Network Computation Graphs to Accelerated GPU Kernels, Automatically.

, , , , , , , , and . ACM Trans. Archit. Code Optim., 16 (4): 38:1-38:26 (2020)

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Joint scheduling and layout optimization to enable multi-level vectorization, , , and . IMPACT, Paris, France, (2012)Diagonal Rescaling For Neural Networks., , and . CoRR, (2017)MLIR: Scaling Compiler Infrastructure for Domain Specific Computation., , , , , , , , , and . CGO, page 2-14. IEEE, (2021)Structured Operations: Modular Design of Code Generators for Tensor Compilers., , , , , , , , , and 2 other author(s). LCPC, volume 13829 of Lecture Notes in Computer Science, page 141-156. Springer, (2022)Memory reuse optimizations in the R-Stream compiler., , , and . GPGPU@ASPLOS, page 42-53. ACM, (2013)Fast Convolutional Nets With fbfft: A GPU Performance Evaluation., , , , , and . ICLR, (2015)The Next 700 Accelerated Layers: From Mathematical Expressions of Network Computation Graphs to Accelerated GPU Kernels, Automatically., , , , , , , , and . ACM Trans. Archit. Code Optim., 16 (4): 38:1-38:26 (2020)TinyIREE: An ML Execution Environment for Embedded Systems from Compilation to Deployment., , , , , and . CoRR, (2022)Code Generation for In-Place Stencils., , , , , and . CGO, page 2-13. ACM, (2023)A Tale of Three Runtimes., , , , , , and . CoRR, (2014)