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A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications.

, , , , , and . IEEE J. Solid State Circuits, 44 (8): 2193-2201 (2009)

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A Fractional-N PLL With Space-Time Averaging for Quantization Noise Reduction., , , , , , , , and . IEEE J. Solid State Circuits, 55 (3): 602-614 (2020)A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications., , , , , and . IEEE J. Solid State Circuits, 44 (8): 2193-2201 (2009)A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops., , , , , , and . IEEE J. Solid State Circuits, 44 (11): 2922-2934 (2009)A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering., , , , and . ISSCC, page 346-347. IEEE, (2008)A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider., , , and . ISCAS, page 3051-3054. IEEE, (2007)A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation., , , , , and . ISCAS, page 1179-1182. IEEE, (2013)A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications., , , , , and . CICC, page 753-756. IEEE, (2008)An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators., , , and . IEEE J. Solid State Circuits, 44 (9): 2426-2436 (2009)A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation., , , , and . ISSCC, page 398-399. IEEE, (2009)