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A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation.

, , , , , , and . IEEE J. Solid State Circuits, 54 (7): 2028-2037 (2019)

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A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 52 (4): 1144-1162 (2017)A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm., , , , , , , , , and . ESSCIRC, page 356-359. IEEE, (2015)An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3756-3768 (2018)A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm., , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1547-1565 (2016)A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS., , , , , , , and . VLSIC, page 1-2. IEEE, (2014)Power saving and noise reduction of 28nm CMOS RF system integration using integrated fan-out wafer level packaging (InFO-WLP) technology., , , , , , , , , and 3 other author(s). 3DIC, page TS6.3.1-TS6.3.4. IEEE, (2015)A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation., , , , , , and . IEEE J. Solid State Circuits, 54 (7): 2028-2037 (2019)Predicting trajectory of crane-lifted load using LSTM network: A comparative study of simulated and real-world scenarios., , , , and . Expert Syst. Appl., (October 2023)A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS., , , , and . IEEE J. Solid State Circuits, 53 (9): 2572-2583 (2018)