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Disambiguation of "Eckerbert, Daniel"

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Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS.

, , , , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1659-1668 (2013)

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Daniel

Daniel

Daniel Dirkmann

In-vitro-Untersuchungen zum Effekt von Hypothermie und Azidose auf Variablen thrombelastometrischer Messungen der Blutgerinnung. Uni Duisburg-Essen, (2009)

Daniel Stanze

Systematische Analyse von Rezeptoren und Effektormechanismen der pulmonalen angeborenen Immunität. Uni Marburg, (2009)

Daniel Wied

Zivilprozessuale Qualifikationsprobleme im Spannungsfeld von Vertrag und Delikt: ein Beitrag zur Auslegung nationalen Zivilprozessrechts in europäischer Perspektive. Uni Regensburg, (2009)
 

Other publications of authors with the same name

Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (7): 1659-1668 (2013)Toward architecture-based test-vector generation for timing verification of fast parallel multipliers., , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 370-379 (2006)A deep submicron power estimation methodology adaptable to variations between power characterization and estimation., and . ASP-DAC, page 716-719. ACM, (2003)Complex IF harmonic rejection mixer for non-contiguous dual carrier reception in 65 nm CMOS., , , , , , , , , and . ESSCIRC, page 357-360. IEEE, (2012)Interconnect-Driven Short-Circuit Power Modeling., and . DSD, page 414-421. IEEE Computer Society, (2001)A receiver for LTE Rel-11 and beyond supporting non-contiguous carrier aggregation., , , , , , , , , and 1 other author(s). ISSCC, page 336-337. IEEE, (2013)A 4.75-34.75 MHz digitally tunable active-RC LPF for >60dB mean RX IRR in 65nm CMOS., , , , , , , , , and . ESSCIRC, page 470-473. IEEE, (2012)Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects., , , and . ISVLSI, page 225-230. IEEE Computer Society, (2003)Cycle-true leakage current modeling for CMOS gates., and . ISCAS (5), page 507-510. IEEE, (2001)A power cut-off technique for gate leakage suppression CMOS logic circuits., , , and . ESSCIRC, page 171-174. IEEE, (2004)