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A built-in supply current test circuit for electrical interconnect tests of 3D ICs., , , and . 3DIC, page 1-6. IEEE, (2014)Yield enhancement techniques for 3-dimensional random access memories., , and . Microelectron. Reliab., 52 (6): 1065-1070 (2012)Efficient test and repair architectures for 3D TSV-based random access memories., , , and . VLSI-DAT, page 1-4. IEEE, (2013)Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs., , , and . VLSI-DAT, page 1-4. IEEE, (2015)Combinational circuit fault diagnosis using logic emulation., , , , and . ISCAS (5), page 549-552. IEEE, (2003)A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume., , , , and . ISCIT, page 1-5. IEEE, (2017)Design-for-testability and fault-tolerant techniques for FFT processors., , and . IEEE Trans. Very Large Scale Integr. Syst., 13 (6): 732-741 (2005)Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults., , , , , and . J. Inf. Sci. Eng., 19 (4): 571-587 (2003)Fault-Aware Dependability Enhancement Techniques for Phase Change Memory., , , , and . J. Electron. Test., 37 (4): 503-513 (2021)Fault-Aware Dependability Enhancement Techniques for Flash Memories., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (3): 634-645 (2020)